The present invention is directed to a method for manufacturing a MESFET comprising self-aligned gate. More specifically, the present invention is directed to the manufacture of a MESFET having a self-aligned gate comprising a first metal layer, a second metal layer as the gate metal, a first dielectric layer, a first spacer and a second spacer, wherein implantation, mask, anisotropic etching, and lift off techniques, as well as, curing process are employed.
An increasingly number of processes have been developed wherein the gate is formed in the manufacture of MESFET components in self-aligning fashion, particularly within the framework of GaAs technology. Manufacturing methods wherein the source and drain regions are also formed in a self-aligning fashion, in addition to the gate region, are of special significance and interest.
The goal of a complete self-alignment wherein the metal contacts for source, drain, and gate are also applied in self-aligning fashion is to reduce the source-to-drain spacing in comparison to the traditional techniques. The goal is also to reduce the gate length down to approximately 0.1 .mu.m given the simultaneous utilization of optical lithography. The source-to-gate spacing or, respectively, the spacing between the n.sup.+ doped region and the gate, as well, as the shorter gate length therewith simultaneously achieved, leads to lower resistances and capacitances, this has a very advantageous effect on the high frequency compatibility.
An overview of the currently used standard manufacturing processes of MESFET gates is provided in an article by C. E. Weitzel and D. A. Doane, "A Review of GaAs MESFET Gate Electrode Fabrication Technologies" in Journal of the Electrochemical Society 133, pages 409C through 416C (1986).
IBM Technical Disclosure Bulletin 28, pages 916 through 917 (1985), describes the manufacture of a MESFET wherein source and drain regions and their respective metallizations are manufactured self-aligned. Standard technologies such as molecular beam epitaxy or chemical vapor deposition (CVD), and ion etching are thereby applied. A channel layer of n-doped GaAs is epitaxially grown on a substrate of semi-insulating GaAs. What is referred to as a contact layer of highly n-conductively doped GaAs then follows, forming the source and drain regions. The metal layer that forms the electrodes for the contacting is subsequently applied and is covered from above with an insulator layer of, for example, SiO.sub.2. A trench is etched out through the contact layer, through the metal layer, and through the insulator layer. The side walls of the trench are provided with spacer regions (spacers) in a further process step. The metal of the gate metallization is applied between these spacers; these are referred to as "side walls" in the publication.
As an alternative embodiment, the authors propose that the application of the channel layer be forgone and the doping required for the channel region be instead introduced into the substrate by ion implantation before the application of the spacers. This manufacturing process involves the considerable disadvantage that an additional expitaxial step is required for the formation of the highly n-conductively doped source and drain regions. The application of the channel layer requires a further epitaxial step or the channel region must be created by subsequent ion implantation; this then requires high-temperature-stable metallizations because of the curing process that is required. No teaching can be derived from the publication whether this subsequent formation of the channel region supplies a usable junction between this channel region and the highly doped source and drain regions. Some structuring or other of the channel region is not provided.
U.S. Pat. No. 4,472,872 discloses a method wherein an active layer is applied to a GaAs substrate by doping and a layer sequence of gold-germanium alloy as a metal layer for the ohmic contacting and aluminum that is interrupted by a trench is applied on the active layer with lift-off technique. Spacers are then created on the sides of the trench and, after removal of the aluminum layer, a platinum layer is applied for outer contacting, whereby the spacers are simultaneously intended to effect the interruption between source, gate, and drain contact. In a last step, the spacers are removed, as well as part of the gate metal together with the spacers. A n.sup.+ -doping of the source and drain regions is not possible in this method.
European patent application 87102395.8 discloses a method wherein a contact layer of metal and a dielectric layer are applied onto a substrate. A trench-shaped recess comprising a masking element with under-cut shape is achieved. Spacers are subsequently created by anisotropic etching of a further dielectric layer that is isotropically applied surface-wide. The gate metal is applied between these spacers. Depending on the doping process utilized, a depression can be etched into the substrate surface in order to constrict the channel region before the deposition of the gate metal.
Through the dummy gate technique, a dummy gate is first deposited, and serves as an implantation mask. The dummy gate is replaced by a gate metal after further process steps. This technique is self-aligning with respect to the source, drain, and gate regions, but not with respect to the corresponding contact metals.
The spacer technique of NEC, eliminates the n.sup.+ -regions, because the metal for the ohmic contacts move toward the gate edges self-aligned. A simple T-gate having large cross-section is not possible, this having a disadvantageous influence on the structure sophistication.
The SAGFET method deriving from a proposal by Fujitsu (M. Yokoyama et al in IEEE ISSCC 1981, pages 218 through 219) has been investigated in various embodiments. They all require a Schottky contact that resists the curing procedure following the implantation, this presents a great problem. This method is self-aligning with respect to the n.sup.+ -implantation and with respect to the gate region.
In the SAINT process, the n.sup.+ implantation is limited by a photoresist structure with a SiO.sub.2 cover layer. After various process steps, the lacquer structure is replaced by the gate metal that is self-aligned with respect to the source and drain regions but not with respect to the source and drain metal contacts. A structural sophistication thereby requires nonlight-optical lithography.